(1) Field of the Invention
The present invention relates to a method of fabricating a dynamic random access memory having a multi-pillared capacitor storage node, and more particularly, a method of fabricating a dynamic random access memory having a multi-pillared capacitor storage node using silylated photoresist.
(2) Description of the Prior Art
In recent years there has been a dramatic increase in the packing density of DRAMs. Large DRAM devices are normally silicon based, and each cell typically embodies a single MOS field effect transistor with its source connected to a storage capacitor. This large integration of DRAMs has been accomplished by a reduction in individual cell size. However, the reduction in cell size results in a decrease in storage capacitance leading to reliability drawbacks, such as a lowering of source/drain ratio and undesirable signal problems. In order to achieve the desired higher level of integration, the technology must keep almost the same storage capacitance on a greatly reduced cell area.
Efforts to maintain or increase the storage capacitance in memory cells with greater packing densities have included the use of a stacked cylindrical capacitor design in which the capacitor cell uses the space over the device area for the capacitor plates. In U.S. Pat. No. 5,436,187 to Tanigawa, a cylindrical capacitor is formed using spacers. U.S. Pat. No. 5,733,808 to Tseng forms a cylindrical capacitor by laterally etching a resist mask and then etching out the central portion of a polysilicon layer. U.S. Pat. No. 5,712,202 to Liaw et al shows a process for a double-walled cylindrical capacitor using spacers and an etch back process. U.S. Pat. Nos. 5,821,139 to Tseng and 5,721,154 to Jeng show processes for forming double-walled cylindrical capacitors using spacers. U.S. Pat. No. 5,753,420 to Misium teaches a process of silylating an unexposed photoresist layer leaving a residue to be used in etching a capacitor plate with peaks. U.S. Pat. No. 5,753,419 to Misium uses silylated photoresist to etch a wave pattern into a polysilicon layer to form a storage node. U.S. Pat. No. 5,362,606 to Hartney et al discloses the use of silylated photoresist to form a pattern. Co-pending U.S. patent application Ser. No. 09/332,424 to Tseng, filed on Jun. 14, 1999, teaches a method of using silylated photoresist to form a storage node having five polysilicon bars.